OR-AND-invert gates or OAI-gates are logic gates comprising OR gates followed by a NAND gate. They can be efficiently implemented in logic families like CMOS and TTL. They are dual to AND-OR-invert gates.
Overview
OR-AND-invert gates implement the inverted product of sums. groups of , input signals combined with OR, and the results then combined with NAND.
Examples
2-1 OAI-gate
A 2-1-OAI gate realizes the function
with the truth table shown below.
| Truth table 2-1 OAI | |||
| Input A B C |
Output Y | ||
| 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 0 |
2-2 OAI gate
A 2-2-OAI gate realizes the function
with the truth table shown below.
| Truth table 2-2 OAI | ||||
| INPUT A B C D |
OUTPUT Q | |||
| 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 0 | 1 | 1 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 | 0 |
Realization
OAI-gates can efficiently be implemented as complex gates. An example of a 3-1 OAI-gate is shown in the figure below.[1]
Examples of use
One possibility of implementing an XOR gate is by using a 2-2-OAI-gate with non-inverted and inverted inputs. [2]
References
- ^ Hendrichs, Norman. "CMOS OAI31 or-and-invert complex gate". University of Hamburg. Retrieved 2024-02-12.
- ^ Fischer, P. "Aussagenlogik und Gatter" (PDF). University of Heidelberg. Retrieved 2024-01-21.